40.8.9 SDHC Present State Register

Table 40-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—


Bit	31	30	29	28	27	26	25	24
								CMDLL
Access								R
Reset								0


Bit	23	22	21	20	19	18	17	16
	DATLL[3:0]				WRPPL	CARDDPL	CARDSS	CARDINS
Access	R	R	R	R	R	R	R	R
Reset	1	1	1	1	1	0	0	0


Bit	15	14	13	12	11	10	9	8
					BUFRDEN	BUFWREN	RTACT	WTACT
Access					R	R	R	R
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
						DLACT	CMDINHD	CMDINHC
Access						R	R	R
Reset						0	0	0

Bit 24 – CMDLL CMD Line Level

This status is used to check the CMD line level to recover from errors, and for debugging.

Bits 23:20 – DATLL[3:0] DAT[3:0] Line Level

This status is used to check the DAT line level to recover from errors, and for debugging. This is especially useful in detecting the Busy signal level from DAT[0].

Bit 19 – WRPPL Write Protect Pin Level

The Write Protect Switch is supported for memory and combo cards. This bit reflects the SDHC_WP pin.

Value	Description
0	Write protected (SDHC_WP = 0)
1	Write enabled (SDHC_WP = 1)

Bit 18 – CARDDPL Card Detect Pin Level

This bit reflects the inverse value of the SDHC_CD pin. Debouncing is not performed on this bit. This bit may be valid when CARDSS is set to 1, but it is not guaranteed because of the propagation delay. Use of this bit is limited to testing since it must be debounced by software.

Value	Description
0	No card present (SDHC_CD = 1)
1	Card present (SDHC_CD = 0)

Bit 17 – CARDSS Card State Stable

This bit is used for testing. If it is 0, the CARDDPL is not stable. If this bit is set to 1, it means that the CARDDPL is stable. No Card state can be detected if this bit is set to 1 and CARDINS is set to 0.

The Software Reset For All (SWRSTALL) in SDHC_SRR does not affect this bit.

Value	Description
0	Reset or debouncing
1	No card or card inserted

Bit 16 – CARDINS Card Inserted

This bit indicates whether a card has been inserted. The peripheral debounces this signal so that the user does not need to wait for it to stabilize.

A change from 0 to 1 rises the Card Insertion (CINS) status flag in SDHC_NISTR if SDHC_NISTER.CINS is set to 1. An interrupt is generated if SDHC_NISIER.CINS is set to 1.

A change from 1 to 0 rises the Card Removal (CREM) status flag in SDHC_NISTR if SDHC_NISTER.CREM is set to 1. An interrupt is generated if SDHC_NISIER.CREM is set to 1.

The Software Reset For All (SWRSTALL) in SDHC_SRR does not affect this bit.

Bit 11 – BUFRDEN Buffer Read Enable

This bit is used for non-DMA read transfers. This flag indicates that valid data exists in the peripheral data buffer. If this bit is 1, readable data exists in the buffer.

A change from 1 to 0 occurs when all the block data is read from the buffer.

A change from 0 to 1 occurs when block data is ready in the buffer. This rises the Buffer Read Ready (BRDRDY) status flag in SDHC_NISTR if SDHC_NISTER.BRDRDY is set to 1. An interrupt is generated if SDHC_NISIER.BRDRDY is set to 1.

Bit 10 – BUFWREN Buffer Write Enable

This bit is used for non-DMA write transfers. This flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer.

A change from 1 to 0 occurs when all the block data are written to the buffer.

A change from 0 to 1 occurs when top of block data can be written to the buffer. This rises the Buffer Write Ready (BRWRDY) status flag in SDHC_NISTR if SDHC_NISTER.BRWRDY is set to 1. An interrupt is generated if SDHC_NISIER.BRWRDY is set to 1.

Bit 9 – RTACT Read Transfer Active

This bit is used to detect completion of a read transfer. Refer to section “Read Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification V3.00” for more details on the sequence of events.

This bit is set to 1 in either of the following conditions:

After the end bit of the read command.
When a read operation is restarted by writing a 1 to SDHC_BGCR.CONTR (Continue Request).

This bit is cleared to 0 in either of the following conditions:

When the last data block as specified by Transfer Block Size (BLKSIZE) is transferred to the system.
In case of ADMA2, end of read is designated by the descriptor table.
When all valid data blocks in the peripheral have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request (STPBGR) of SDHC_BGCR being set to 1.

A change from 1 to 0 rises the Transfer Complete (TRFC) status flag in SDHC_NISTR if SDHC_NISTER.TRFC is set to 1. An interrupt is generated if SDHC_NISIER.TRFC is set to 1.

Bit 8 – WTACT Write Transfer Active

This bit indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the peripheral. Refer to section “Write Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification V3.00” for more details on the sequence of events.

This bit is set to 1 in either of the following conditions:

After the end bit of the write command.
When a write operation is restarted by writing a 1 to SDHC_BGCR.CONTR (Continue Request).

This bit is cleared to 0 in either of the following conditions:

After getting the CRC status of the last data block as specified by the transfer count (single and multiple). In case of ADMA2, transfer count is designated by the descriptor table.
After getting the CRC status of any block where a data transmission is about to be stopped by a Stop At Block Gap Request (STPBGR) of SDHC_BGCR.

During a write transaction and as the result of the Stop At Block Gap Request (STPBGR) being set, a change from 1 to 0 rises the Block Gap Event (BLKGE) status flag in SDHC_NISTR if SDHC_NISTER.BLKGE is set to 1. An interrupt is generated if BLKGE is set to 1 in SDHC_NISIER. This status is useful to determine whether non-DAT line commands can be issued during Write Busy.

Bit 2 – DLACT DAT Line Active

This bit indicates whether one of the DAT lines on the bus is in use.

In the case of read transactions:

This status indicates whether a read transfer is executing on the bus. A change from 1 to 0 resulting from setting the Stop At Block Gap Request (STPBGR) rises the Block Gap Event (BLKGE) status flag in SDHC_NISTR if SDHC_NISTER.BLKGE is set to 1. An interrupt is generated if SDHC_NISIER.BLKGE is set to 1. Refer to section “Read Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification V3.00” for details on timing.

This bit is set in either of the following cases:

After the end bit of the read command.
When writing 1 to SDHC_BGCR.CONTR (Continue Request) to restart a read transfer.

This bit is peripheral cleared in either of the following cases:

When the end bit of the last data block is sent from the bus to the peripheral. In case of ADMA2, the last block is designated by the last transfer of the Descriptor Table.
When a read transfer is stopped at the block gap initiated by a Stop At Block Gap Request (STPBGR).

The peripheral stops a read operation at the start of the interrupt cycle by driving the Read Wait (DAT[2] line) or by stopping the SD Clock. If the Read Wait signal is already driven (due to the fact that the data buffer cannot receive data), the peripheral can continue to stop the read operation by driving the Read Wait signal. It is necessary to support the Read Wait in order to use the Suspend/Resume operation.

In the case of write transactions:

This status indicates that a write transfer is executing on the bus. A change from 1 to 0 rises the Transfer Complete (TRFC) status flag in SDHC_NISTR if SDHC_NISTER.TRFC is set to 1. An interrupt is generated if SDHC_NISIER.TRFC is set to 1. Refer to section “Write Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification V3.00” for details on timing.

This bit is set in either of the following cases:

After the end bit of the write command.
When writing 1 to SDHC_BGCR.CONTR (Continue Request) to continue a write transfer.

This bit is cleared in either of the following cases:

When the card releases Write Busy of the last data block. If the card does not drive a Busy signal for 8 SDCLK, the peripheral considers the card drive “Not Busy”. In the case of ADMA2, the last block is designated by the last transfer of the Descriptor Table.
When the card releases Write Busy prior to wait for write transfer as a result of a Stop At Block Gap Request (STPBGR).

Command with Busy:

This status indicates whether a command that indicates Busy (ex. erase command for memory) is executing on the bus. This bit is set to 1 after the end bit of the command with Busy and cleared when Busy is de-asserted. A change from 1 to 0 rises the Transfer Complete (TRFC) status flag in SDHC_NISTR if SDHC_NISTER.TRFC is set to 1. An interrupt is generated if SDHC_NISIER.TRFC is set to 1. Refer to Figures 2.11 to 2.13 in the “SD Host Controller Simplified Specification V3.00”.

Value	Description
0	DAT Line Inactive
1	DAT Line Active

Bit 1 – CMDINHD Command Inhibit (DAT)

This status bit is 1 if either the DAT Line Active (DLACT) or the Read Transfer Active (RTACT) is set to 1. If this bit is 0, it indicates that the peripheral can issue the next command. Commands with a Busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). A change from 1 to 0 rises the Transfer Complete (TRFC) status flag in SDHC_NISTR if SDHC_NISTER.TRFC is set to 1. An interrupt is generated if SDHC_NISIER.TRFC is set to 1.

Note: The software can save registers in the 000-00Dh range for a suspend transaction after this bit has changed from 1 to 0.

Value	Description
0	Can issue a command which uses the DAT line(s).
1	Cannot issue a command which uses the DAT line(s).

Bit 0 – CMDINHC Command Inhibit (CMD)

If this bit is 0, it indicates the CMD line is not in use and the peripheral can issue a command using the CMD line. This bit is set to 1 immediately after SDHC_CR is written. This bit is cleared when the command response is received. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the CMD12 or CMD23 response, but by the Read/Write command response.

Status issuing Auto CMD12 is not read from this bit. So, if a command is issued during Auto CMD12 operation, the peripheral manages to issue both commands: CMD12 and a command set by SDHC_CR.

Even if the Command Inhibit (DAT) is set to 1, commands using only the CMD line can be issued if this bit is 0.

A change from 1 to 0 rises the Command Complete (CMDC) status flag in SDHC_NISTR if SDHC_NISTER.CMDC is set to 1. An interrupt is generated if SDHC_NISIER.CMDC is set to 1.

If the peripheral cannot issue the command because of a command conflict error (refer to CMDCRC in SDHC_EISTR) or because of a ‘Command Not Issued By Auto CMD12’ error, this bit remains 1 and Command Complete is not set.

Value	Description
0	Can issue a command using only CMD line.
1	Cannot issue a command.

Name:	PSR
Offset:	0x24
Reset:	0x00F80000
Property:	-