40.8.22 SDHC Error Interrupt Signal Enable Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | EISIER |
| Offset: | 0x3A |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BOOTAE | TUNING | ADMA | ACMD | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CURLIM | DATEND | DATCRC | DATTEO | CMDIDX | CMDEND | CMDCRC | CMDTEO | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 12 – BOOTAE Boot Acknowledge Error Signal Enable
Note: This register entry is specific to the e.MMC operation mode.
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.BOOTAE is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.BOOTAE is set. |
Bit 10 – TUNING Tuning Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.TUNING is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.TUNING is set. |
Bit 9 – ADMA ADMA Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.ADMA is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.ADMA is set. |
Bit 8 – ACMD Auto CMD Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.ACMD is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.ACMD is set. |
Bit 7 – CURLIM Current Limit Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.CURLIM is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.CURLIM is set. |
Bit 6 – DATEND Data End Bit Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.DATEND is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.DATEND is set. |
Bit 5 – DATCRC Data CRC Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.DATCRC is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.DATCRC is set. |
Bit 4 – DATTEO Data Timeout Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.DATTEO is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.DATTEO is set. |
Bit 3 – CMDIDX Command Index Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.CMDIDX is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.CMDIDX is set. |
Bit 2 – CMDEND Command End Bit Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.CMDEND is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.CMDEND is set. |
Bit 1 – CMDCRC Command CRC Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.CMDCRC is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.CMDCRC is set. |
Bit 0 – CMDTEO Command Timeout Error Signal Enable
| Value | Name | Description |
|---|---|---|
| 0 | MASKED | No interrupt is generated when SDHC_EISTR.CMDTEO is set. |
| 1 | ENABLED | An interrupt is generated when SDHC_EISTR.CMDTEO is set. |