25.7 BiSS Communication Configuration Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | B1CCON |
| Offset: | 0x1FE8 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MODELAY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FREQAGS[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:8 – MODELAY[7:0] Delay of Start Bit at Output MOx bits
| Value | Description |
|---|---|
| 11111111-00000001 | Value * 1 /FSCD |
| 00000000 | No start delay |
Bits 7:0 – FREQAGS[7:0] AutoGetSense Frequency - Controls Automatic SCD Timing bits
| Value | Description |
|---|---|
| 0x80-0xFF | CLK/ (625 * (Value+1) |
| 0x7D | AGSINFINITE - Requires trigger event to start next SCD cycle, such as GETSENSE or INSTR |
| 0x7C | AGSMIN - Host automatically restarts the next SCD cycle after the prior finishes |
| 0x00-0x7B | CLK/ (20 * (FREQAGS(6:0)+1)) |