25.11 BiSS Channel Status Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | B1CHSTAT |
| Offset: | 0x1FF8 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BKSWERR | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CDS7 | SL7 | CDS6 | SL6 | CDS5 | SL5 | CDS4 | SL4 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | x | 0 | x | 0 | x | 0 | x |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CDS3 | SL3 | CDS2 | SL2 | CDS1 | SL1 | CDS0 | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | x | 0 | x | 0 | x | 0 |
Bit 24 – BKSWERR Switch Bank Failed bit
| Value | Description |
|---|---|
| 1 | Bank switching (SCD) not successful |
| 0 | Bank switching (SCD) successful |
Bit 15 – CDS7 Channel 7 CDS bit
| Value | Description |
|---|---|
| 1 | CDS7 =
1
|
| 0 | CDS7 =
0 |
Bit 14 – SL7 SL7 Input Line State bit
| Value | Description |
|---|---|
| 1 | SL7 line level high |
| 0 | SL7 line level low |
Bit 13 – CDS6 Channel 6 CDS bit
| Value | Description |
|---|---|
| 1 | CDS6 =
1
|
| 0 | CDS6 =
0 |
Bit 12 – SL6 SL6 Input Line State bit
| Value | Description |
|---|---|
| 1 | SL6 line level high |
| 0 | SL6 line level low |
Bit 11 – CDS5 Channel 5 CDS bit
| Value | Description |
|---|---|
| 1 | CDS5 =
1
|
| 0 | CDS5 =
0 |
Bit 10 – SL5 SL5 Input Line State bit
| Value | Description |
|---|---|
| 1 | SL5 line level high |
| 0 | SL5 line level low |
Bit 9 – CDS4 Channel 4 CDS bit
| Value | Description |
|---|---|
| 1 | CDS4 =
1
|
| 0 | CDS4 =
0 |
Bit 8 – SL4 SL4 Input Line State bit
| Value | Description |
|---|---|
| 1 | SL4 line level high |
| 0 | SL4 line level low |
Bit 7 – CDS3 Channel 3 CDS bit
| Value | Description |
|---|---|
| 1 | CDS3 =
1
|
| 0 | CDS3 =
0 |
Bit 6 – SL3 SL3 Input Line State bit
| Value | Description |
|---|---|
| 1 | SL3 line level high |
| 0 | SL3 line level low |
Bit 5 – CDS2 Channel 2 CDS bit
| Value | Description |
|---|---|
| 1 | CDS2 =
1
|
| 0 | CDS2 =
0 |
Bit 4 – SL2 SL2 Input Line State bit
| Value | Description |
|---|---|
| 1 | SL2 line level high |
| 0 | SL2 line level low |
Bit 3 – CDS1 Channel1 CDS bit
| Value | Description |
|---|---|
| 1 | CDS1 =
1
|
| 0 | CDS1 =
0 |
Bit 2 – SL1 SL1 Input Line State bit
| Value | Description |
|---|---|
| 1 | SL1 line level high |
| 0 | SL1 line level low |
Bit 1 – CDS0 Channel 0 CDS bit
| Value | Description |
|---|---|
| 1 | CDS0 =
1
|
| 0 | CDS0 =
0 |
Bit 1 – SL0 SL0 Input Line State bit
| Value | Description |
|---|---|
| 1 | SL0 line level high |
| 0 | SL0 line level low |