25.6 BiSS Control Communication Configuration Register
Note:
- Bits 11-13 reside within the same bit space but have different uses based on the operation mode. For example, IDADIS and CMD are used during command communication, and CLNTID is used during control communication.
- Behavior is determined by the client.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | B1CTRLCON |
| Offset: | 0x1FE4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NOCRC | BANKSWEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Reserved[2:0] | SFREQ[4:0] | ||||||||
| Access | R | R | R | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CTS | PROTOSEL | IDADISCLNTID0[2:0] | MOEN | HOLDCDM | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHSEL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 25 – NOCRC CRC for SCD Not to be Stored in RAM bit
| Value | Description |
|---|---|
| 1 | All client CRC of SCD not stored in RAM |
| 0 | CRC of SCD is stored in RAM (only applicable with active CRC verification and CRC polynomial > 0) |
Bit 24 – BANKSWEN Single RAM Bank Enabled bit
| Value | Description |
|---|---|
| 1 | One RAM bank is used for SCD |
| 0 | Two RAM banks are used for SCD |
Bits 23:21 – Reserved[2:0]
Read as ‘0’
Bits 20:16 – SFREQ[4:0] Sensor Data Clock Frequency (FSCD) bit
| Value | Description |
|---|---|
| 11111 - 10010 | CLK / 20 / (Value - 15) |
| 10001 | CLK / 40 |
| 10000 | Not permitted |
| 01111 - 00001 | CLK / 2 / (Value + 1) |
| 00000 | CLK/2 |
Bit 15 – CTS Register Transmission or Instruction Selector bit
| Value | Description |
|---|---|
| 1 | Register communication |
| 0 | Command/instruction communication |
Bit 14 – PROTOSEL Register Access Protocol Selection A/B or C Selector bit
| Value | Description |
|---|---|
| 1 | Register communication BiSS C |
| 0 | Reserved |
Bits 13:12 – CMDCLNTID21[1:0] Command bits for command communication/Client ID bit 2 and bit 1 for control communication(1)
| Value | Description |
|---|---|
| 11 | Command value(2)/Bit 2 and bit 1 value of the Client's ID |
| 10 | Command value(2)/Bit 2 and bit 1 value of the Client's ID |
| 01 | Command value(2))/Bit 2 and bit 1 value of the Client's ID |
| 00 | Command value(2)/Bit 2 and bit 1 value of the Client's ID |
Bits 13:11 – IDADISCLNTID0[2:0] Client Selector bit - client ID of accessed client
Bit 11 – IDADISCLNTID0 ID Acknowledge Disable bit for command communication/Client ID bit 0 for control communication(1)
| Value | Description |
|---|---|
| 1 | Immediate execution/Bit 0 value of the Client's ID |
| 0 | Client's feedback (IDA) is checked before execution (EX bit after IDA)/Bit 0 value of the Client's ID |
Bit 9 – MOEN MO Enable - Enable Output at MOx for Actuator Data or Delayed Start bit
| Value | Description |
|---|---|
| 1 | Parameterized processing time by host when MO signal active (length = MODELAY) |
| 0 | MO forced to low |
Bit 8 – HOLDCDM Hold CDM (Control Data Host) - Length of CDM bit
| Value | Description |
|---|---|
| 1 | Clock line consistent with CDM bit until start of next cycle |
| 0 | Clock line high at end of cycle |
Bits 7:0 – CHSEL[7:0] Channel Selection bit
| Value | Description |
|---|---|
| 1 | Channel N used for communication |
| 0 | Channel N not used for communication |
