AN4597

1.3.2.3.1 DDR3L

The DDR3L subsystem is configured to access the 16-bit DDR3L memory through an AXI4 interface. The “PolarFire® Evaluation kit DDR3L memory” preset is applied to configure all of the memory initialization and timing parameters in the DDR3L configurator.

Important:

DDR3L is applicable only for Evaluation kit demo design.
For more information about Rev E or later kit DDR3L Configurations (MT41K512M8DA-107: P), see Appendix 3 - DDR3 Configuration of the AN4997: PolarFire FPGA Building a Mi-V Processor Subsystem.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.