7.7.2 PIR0

Peripheral Interrupt Request (Flag) Register 0
Note:
  1. The External Interrupt INT pin is selected by INTPPS.
  2. The IOCIF bit is the logical OR of all the IOCAF-IOCEF flags. Therefore, to clear the IOCIF flag, application firmware must clear all of the lower level IOCAF-IOCEF register bits.
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an interrupt.
Name: PIR0
Address: 0x70C

Bit 76543210 
   TMR0IFIOCIF   INTF 
Access R/W/HSROR/W/HS 
Reset 000 

Bit 5 – TMR0IF  Timer0 Interrupt Flag bit

ValueDescription
1 TMR0 register has overflowed (must be cleared by software)
0 TMR0 register has not overflowed

Bit 4 – IOCIF  Interrupt-on-Change Flag bit(2)

ValueDescription
1 One or more of the IOCAF-IOCEF register bits are currently set, indicating an enabled edge was detected by the IOC module.
0 None of the IOCAF-IOCEF register bits are currently set

Bit 0 – INTF  External Interrupt Flag bit(1)

ValueDescription
1 External Interrupt has occurred
0 External Interrupt has not occurred
The External Interrupt INT pin is selected by INTPPS. The IOCIF bit is the logical OR of all the IOCAF-IOCEF flags. Therefore, to clear the IOCIF flag, application firmware must clear all of the lower level IOCAF-IOCEF register bits. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an interrupt.