7.7.7 PIR5
Peripheral Interrupt Request (Flag) Register 5
Note: Interrupt flag bits are
set when an interrupt condition occurs, regardless of the state of
its corresponding enable bit or the Global Enable bit, GIE, of the
INTCON appropriate interrupt flag bits are clear prior to enabling
an interrupt.
| Name: | PIR5 |
| Address: | 0x711 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLC4IF | CLC3IF | CL24IF | CLC1IF | TMR5GIF | TMR3GIF | TMR1GIF | |||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – CLC4IF CLC4 Interrupt Flag bit
| Value | Description |
|---|---|
1 |
A CLC4OUT Interrupt condition has occurred (must be cleared in software) |
0 |
No CLC4 interrupt event has occurred |
Bit 6 – CLC3IF CLC3 Interrupt Flag bit
| Value | Description |
|---|---|
1 |
A CLC3OUT Interrupt condition has occurred (must be cleared in software) |
0 |
No CLC3 interrupt event has occurred |
Bit 5 – CL24IF CLC2 Interrupt Flag bit
| Value | Description |
|---|---|
1 |
A CLC2OUT Interrupt condition has occurred (must be cleared in software) |
0 |
No CLC2 interrupt event has occurred |
Bit 4 – CLC1IF CLC1 Interrupt Flag bit
| Value | Description |
|---|---|
1 |
A CLC1OUT Interrupt condition has occurred (must be cleared in software) |
0 |
No CLC1 interrupt event has occurred |
Bit 2 – TMR5GIF TMR5 Gate Interrupt Flag bit
| Value | Description |
|---|---|
1 |
The Timer5 Gate has gone Inactive (the acquisition is complete) |
0 |
The Timer5 Gate has not gone Inactive |
Bit 1 – TMR3GIF TMR3 Gate Interrupt Flag bit
| Value | Description |
|---|---|
1 |
The Timer3 Gate has gone Inactive (the acquisition is complete) |
0 |
The Timer3 Gate has not gone Inactive |
Bit 0 – TMR1GIF TMR1 Gate Interrupt Flag bit
| Value | Description |
|---|---|
1 |
The Timer1 Gate has gone Inactive (the acquisition is complete) |
0 |
The Timer1 Gate has not gone Inactive |