7.7.18 PIE7
Peripheral Interrupt Enable Register 7
Note: Bit PEIE of the
INTCON register must be set to enable any peripheral interrupt
controlled by registers PIE1-PIE8.
Name: | PIE7 |
Address: | 0x71D |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NVMIE | NCO1IE | CWG3IE | CWG2IE | CWG1IE | |||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit 5 – NVMIE NVM Interrupt Enable bit
Value | Description |
---|---|
1 |
Enabled |
0 |
Disabled |
Bit 4 – NCO1IE NCO Interrupt Enable bit
Value | Description |
---|---|
1 |
Enabled |
0 |
Disabled |
Bit 2 – CWG3IE CWG3 Interrupt Enable bit
Value | Description |
---|---|
1 |
Enabled |
0 |
Disabled |
Bit 1 – CWG2IE CWG2 Interrupt Enable bit
Value | Description |
---|---|
1 |
Enabled |
0 |
Disabled |
Bit 0 – CWG1IE CWG1 Interrupt Enable bit
Value | Description |
---|---|
1 |
Enabled |
0 |
Disabled |