7.7.6 PIR4
Peripheral Interrupt Request (Flag) Register 4
Note: Interrupt flag bits are
set when an interrupt condition occurs, regardless of the state of
its corresponding enable bit or the Global Enable bit, GIE, of the
INTCON appropriate interrupt flag bits are clear prior to enabling
an interrupt.
| Name: | PIR4 |
| Address: | 0x710 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TMR6IF | TMR5IF | TMR4IF | TMR3IF | TMR2IF | TMR1IF | ||||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – TMR6IF TMR6 to PR6 Match Interrupt Flag bit
| Value | Description |
|---|---|
1 |
The TMR6 postscaler overflowed, or in 1:1 mode, a TMR6 to PR6 match occurred (must be cleared in software) |
0 |
No TMR6 event has occurred |
Bit 4 – TMR5IF TMR5 Overflow Interrupt Flag bit
| Value | Description |
|---|---|
1 |
TMR5 register overflowed (must be cleared in software) |
0 |
TMR5 register did not overflow |
Bit 3 – TMR4IF TMR4 to PR4 Match Interrupt Flag bit
| Value | Description |
|---|---|
1 |
The TMR4 postscaler overflowed, or in 1:1 mode, a TMR4 to PR4 match occurred (must be cleared in software) |
0 |
No TMR4 event has occurred |
Bit 2 – TMR3IF TMR3 Overflow Interrupt Flag bit
| Value | Description |
|---|---|
1 |
TMR3 register overflowed (must be cleared in software) |
0 |
TMR3 register did not overflow |
Bit 1 – TMR2IF TMR2 to PR2 Match Interrupt Flag bit
| Value | Description |
|---|---|
1 |
The TMR2 postscaler overflowed, or in 1:1 mode, a TMR2 to PR2 match occurred (must be cleared in software) |
0 |
No TMR2 event has occurred |
Bit 0 – TMR1IF TMR1 Overflow Interrupt Flag bit
| Value | Description |
|---|---|
1 |
TMR1 register overflowed (must be cleared in software) |
0 |
TMR1 register did not overflow |