37.4.7 I3CxBSTAT

Note:

Will not self-clear after the event. The user must clear this bit to re-arm.
Refer to the Error Detection and Recovery in SDR Mode section for TE0-TE6 Error definitions.
In case of a race condition, user writes always take precedence over hardware events.

Name:	I3CxBSTAT
Address:	0x089, 0x0BC

Bus Status


Bit	7	6	5	4	3	2	1	0
		TE6ERR	TE5ERR	TE4ERR	TE3ERR	TE2ERR	TE1ERR	TE0ERR
Access		R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS
Reset		0	0	0	0	0	0	0

Bit 6 – TE6ERR TE6 Error Detection⁽¹⁾

Value	Description
1	TE6 Error detected
0	TE6 Error not detected

Bit 5 – TE5ERR TE5 Error Detection⁽¹⁾

Value	Description
1	TE5 Error detected
0	TE5 Error not detected

Bit 4 – TE4ERR TE4 Error Detection⁽¹⁾

Value	Description
1	TE4 Error detected
0	TE4 Error not detected

Bit 3 – TE3ERR TE3 Error Detection⁽¹⁾

Value	Description
1	TE3 Error detected
0	TE3 Error not detected

Bit 2 – TE2ERR TE2 Error Detection⁽¹⁾

Value	Description
1	TE2 Error detected
0	TE2 Error not detected

Bit 1 – TE1ERR TE1 Error Detection⁽¹⁾

Value	Description
1	TE1 Error detected
0	TE1 Error not detected

Bit 0 – TE0ERR TE0 Error Detection⁽¹⁾

Value	Description
1	TE0 Error detected
0	TE0 Error not detected

Will not self-clear after the event. The user must clear this bit to re-arm. Refer to the Error Detection and Recovery in SDR Mode section for TE0-TE6 Error definitions. In case of a race condition, user writes always take precedence over hardware events.