37.4.2 I3CxCON1

Note:
  1. User should use discretion when forcing the module out of HDR mode. Improper usage of this bit may result in unexpected behavior. This bit is ignored when the module is in SDR mode (OPMD = 0b0x). The bit self-clears when HDR to SDR mode transition is complete.
  2. Refer to the Static Address SDR Mode section for more information.
  3. Self-clears after an ACK is sent in response to a Private/I2C Write/Read request. Refer to the Private Transaction section for more information.
  4. In case of a race condition, user writes always take precedence over hardware events.
Name: I3CxCON1
Address: 0x084, 0x0B7

Control 1

Bit 76543210 
     BERRDETFHDRESASDRMDACKPOS 
Access R/WR/W/HCR/WR/W/HC 
Reset 0000 

Bit 3 – BERRDET  Bus Error Detection

ValueDescription
1 The module detects TE0 and TE1 error conditions only in I3C mode of operation (OPMD = 0bx1)
0 The module always detects TE0 and TE1 error conditions regardless of the mode of operation

Bit 2 – FHDRE  Force HDR Exit(1)

ValueDescription
1 Force the module to exit HDR mode and go back to SDR mode
0 A Force HDR Exit has not been initiated or was completed

Bit 1 – SASDRMD  Static Address Single Data Rate (SDR) Mode(2)

ValueDescription
1 The I3C Target module is forced to operate in I3C SDR mode using Static Address if Dynamic Address is not available
0 The I3C Target module operates as usual and transitions to I3C SDR mode upon receiving a Dynamic Address

Bit 0 – ACKPOS  Private Transaction Acknowledge One-shot(3)

ValueNameDescription
X ACKP = 0 This bit is ignored
1 ACKP = 1 The next Private/I2C Write/Read request will be ACK'd when an address match occurs
0 ACKP = 1 The next Private/I2C Write/Read request will be NACK'd
User should use discretion when forcing the module out of HDR mode. Improper usage of this bit may result in unexpected behavior. This bit is ignored when the module is in SDR mode (OPMD Operating Mode Status = 0b0x). The bit self-clears when HDR to SDR mode transition is complete. Refer to the Static Address SDR Mode section for more information. Self-clears after an ACK is sent in response to a Private/I2C Write/Read request. Refer to the Private Transaction section for more information. In case of a race condition, user writes always take precedence over hardware events.