37.4.44 I3CxI2CCON

Note:
  1. The 50 ns Spike Filters can only be used with I2C/SMBus-compatible and Standard GPIO buffers and not with any of the I3C buffers.
  2. These bits are intended to support the Legacy I2C operation, but are effective regardless of the current operating status reflected in the OPMD bits. Enabling these bits while the module is operating in I3C SDR mode (OPMD = 0b01) will cause the module to become incompatible with the MIPI I3C Specification.
Name: I3CxI2CCON
Address: 0x0B4, 0x0E7

Legacy I2C Control

Bit 76543210 
 FLTENSDAHT[1:0] 
Access R/WR/WR/W 
Reset 000 

Bit 2 – FLTEN  Spike Filter Enable(1)

ValueDescription
1 50 ns Spike Filters on SCL and SDA are enabled
0 50 ns Spike Filters on SCL and SDA are disabled

Bits 1:0 – SDAHT[1:0] SDA Hold Time Selection

ValueDescription
11 Minimum 300 ns hold time on SDA after falling edge of SCL
10 Minimum 100 ns hold time on SDA after falling edge of SCL
01 Minimum 30 ns hold time on SDA after falling edge of SCL
00 No hold time on SDA after falling edge of SCL
The 50 ns Spike Filters can only be used with I2C/SMBus-compatible and Standard GPIO buffers and not with any of the I3C buffers. These bits are intended to support the Legacy I2C operation, but are effective regardless of the current operating status reflected in the OPMD Operating Mode Status bits. Enabling these bits while the module is operating in I3C SDR mode (OPMD = 0b01) will cause the module to become incompatible with the MIPI I3C Specification.