2.1.2 ASB Port List

All signals are active high unless stated otherwise. The tables below list the ports generated by the Analog System Builder and explain the function of each signal.

Table 2-2. Analog System Builder Port List
Name	Type	Description
SYS_CLK	INPUT	System clock input for the Analog Block (AB) and analog system soft IP blocks.
SYS_RESET	INPUT	Active‑low asynchronous reset.
VAREF	INOUT	Voltage reference port. Connects to an external voltage when using an external voltage reference. Returns the internal voltage reference when using the internal voltage reference. This port must be connected to a top‑level port without any additional I/O buffers.
Analog Input Channels	INPUT	User‑specified port names. Analog input channels that are enabled and used in the system.
Analog Output Channels	OUTPUT	User‑specified port names. Analog output channels that are enabled and used in the system.
Input Channel Compare Flags	OUTPUT	Threshold comparison flags generated for each configured peripheral.

Table 2-3. Flash Memory Block Interface
Name	Type	Description
INIT_DATA[8:0]	INPUT	Initialization data input.
INIT_DONE	INPUT	Initialization‑complete signal from the Flash Memory Block (FMB).
INIT_ACM_WEN	INPUT	Initialization Analog Configuration multiplexer (ACM) write enable.
INIT_ASSC_WEN	INPUT	Initialization Analog Sample Sequence Controller (ASSC) RAM write enable.
INIT_EV_WEN	INPUT	Initialization Sample Monitor and Evaluation Block (SMEV) RAM write enable.
INIT_TR_WEN	INPUT	Initialization Sample Monitor and Threshold Block (SMTR) RAM write enable.
INIT_ACM_RTC_WEN	INPUT	ACM initialization write enable during the second initialization pass. This signal is exported only when the Real Time Counter (RTC) peripheral is used.

Table 2-4. Status Signals
Name	Type	Description
DATAVALID	OUTPUT	Indicates that valid data from the Analog‑to‑Digital converter (ADC) is available.
ASSC_DONE	OUTPUT	Indicates that the ASSC has completed processing the current sampling slot.
ASSC_WAIT	OUTPUT	Indicates that the ASSC is inserting wait states to accommodate SMEV and SMTR processing times.
ASSC_CHSAT	OUTPUT	Sampled‑channel saturated indicator. Indicates that the channel sampled by the ADC is saturated (exceeds the ADC voltage range). Once asserted, this signal remains active until the next timeslot is processed. If this signal is asserted, a higher voltage range may be required (for example, by decreasing the prescaler value for the affected analog input pad).
ASSC_CHLATD	OUTPUT	Channel‑selector latched indicator. Indicates that the ADC channel selector value (ADC_CHNR[4:0]) has been latched.