2.1.1 Analog System Builder Reference
The Analog System Builder uses some terminologies that may be unfamiliar. The table below lists the terms and acronyms found in the software and the help documentation.
| Term | Description |
|---|---|
| ADC | Analog‑to‑Digital Converter |
| ASSC | Analog Sample Sequence Controller; it sets the sample order in the Analog-to-Digital Converter (ADC) and includes intellectual property (IP) logic and Random Access Memory (RAM). |
| Analog System | The complete system, which includes the analog block (AB) hard IP and one or more ASSC, sample monitor and evaluation blocks (SMEV), and sample monitor and threshold blocks (SMTR) soft IP blocks. |
| SMEV | Sample Monitor and Evaluation Block that evaluates converted analog data and includes IP logic and RAM. |
| SMTR | Sample Monitor and Threshold block that processes evaluated analog data and generates flag signals under specified conditions; it includes IP logic and RAM. |
| AB | Analog Block. The hard macro in the CAE library that includes the analog multiplexer (MUX) and the ADC. |
| Analog MUX | The 32‑to‑1 MUX whose select signals determine the channel sampled by the ADC. |
| ACM | Analog Configuration Multiplexer that stores configuration data related to analog channels, such as channel type, prescaler value, and polarity. |
| FMSB | Flash Memory System Builder. |
| INIT IP | INIT/CFG soft IP responsible for all initialization and save operations to the nonvolatile memory (NVM). |
| ASB | Analog System Block. The top level of the analog system that includes the AB and analog system soft IP blocks. |
| FMB | Flash memory block. The top level that includes the Flash Memory System Builder and INIT IP. |
| FASTCLK | Clock intended for use during normal system execution. |
| SLOWCLK | Clock intended for use during system initialization. |