10.4.7.3 Synchronous Dual Port FIFO without Flags Implementation Rules/Timing Diagrams
The following table lists the implementation rules for a Synchronous Dual Port FIFO.
| Term | Description |
|---|---|
| tckhl | Clock high/low period |
| trp | Reset pulse width |
| twesu | Write enable setup time |
| tresu | Read enable setup time |
| tdsu | Data setup time |
| trco | Data valid after clock high/low |
| tco | Flip-flop to clock output |
The following figures illustrate the timing diagrams for a Synchronous Dual Port FIFO without Flags.
