10.4.11 RAM Content Manager Summary

Related Topics

The RAM Content Manager enables you to specify the contents of your memory so that you can avoid the simulation cycles required for initializing the memory, which reduces simulation runtime.

For Fusion families, the RAM Content Manager also enables you to specify the RAM content that is loaded into the Flash Memory System Builder.

The RAM core generator takes away much of the complexity required in the generation of large RAMs that utilize one or more RAM blocks on the device. The configurator uses one or more memory blocks to generate a RAM matching your configuration and creates the surrounding cascading logic.

The configurator cascades RAM blocks in three different ways:

  • Cascaded deep (for example 2 blocks of 4096x1 to create a 8192x1)
  • Cascaded wide (for example 2 blocks of 4096x1 to create a 4096x2)
  • Cascaded wide and deep (for example 4 blocks of 4096x1 to create a 8192x2, in a 2 blocks width-wise by 2 blocks depth-wise configuration)

You specify memory content in terms of your total memory size. The configurator must partition your memory file appropriately such that the right content goes to the right block RAM when multiple blocks are cascaded.

Supported Formats

Microchip® implementation of these formats interprets data sets in bytes. This means that if the memory width is 7 bits, every 8th bit in the data set is ignored. Or, if the data width is 9, two bytes are assigned to each memory address and the upper 7 bits of each 2-byte pair are ignored.

The following examples illustrate how the data is interpreted for various word sizes.

For the given data: FF 11 EE 22 DD 33 CC 44 BB 55 (where 55 is the MSB and FF is the LSB)

For 32-bit word size:


                0x22EE11FF (address 0)
                0x44CC33DD (address 1)
                0x000055BB (address 2)

For 16-bit word size:


                0x11FF (address 0)
                0x22EE (address 1)
                0x33DD (address 2)
                0x44CC (address 3)
                0x55BB (address 4)

For 8-bit word size:


                0xFF (address 0)
                0x11 (address 1)
                0xEE (address 2)
                0x22 (address 3)
                0xDD (address 4)
                0x33 (address 5)
                0xCC (address 6)
                0x44 (address 7)
                0xBB (address 8)
                0x55 (address 9)

For 9-bit word size:


                0x11FF -> 0x01FF (address 0)
                0x22EE -> 0x00EE (address 1)
                0x33DD -> 0x01DD (address 2)
                0x44CC -> 0x00CC (address 3)
                0x55BB -> 0x01BB (address 4)
Note: 9-bit word size, the upper 7 bits of the 2-byte pairs are ignored.