10.4.13 Synchronous/Asynchronous Dual Port RAM for DX/MX
This core provides dual-port RAM functionality supporting synchronous and asynchronous read and write operations for DX and MX devices.
Related Topics
Key Features
- Parameterized word length and depth
- Dual port synchronous RAM architecture
- Dual port synchronous write, asynchronous read RAM architecture
The RAM cores use 3200DX and MX, 32x8 or 64x4, dual port RAM cells.
In the synchronous mode, the read and write operations are totally independent and can be performed simultaneously. The operation of the RAM is fully synchronous with respect to the clock signals, WClock and RClock. Data of value Data are written to the WAddress of the RAM memory space on the rising (RISE) or falling (FALL) edge of the clock signal WClock (WCLK_EDGE). Data are read from the RAM memory space at RAddress into Q on the rising (RISE) or falling (FALL) edge of the clock signal RClock (RCLK_EDGE).
The behavior of the RAM is unknown if you write and read at the same address and signals WClock and RClock are not the same. The output Q of the RAM depends on the time relationship between the write and the read clock.
In the asynchronous mode, the operation of the RAM is only synchronous with respect to the clock signal WClock. Data of value Data are written to the WAddress of the RAM memory space on the rising (RISE) or falling (FALL) edge of the clock signal WClock (WCLK_EDGE). Data are read from the RAM memory space at RAddress into Q after some delay when RAddress has changed.
The behavior of the RAM is unknown if you write and read at the same address. The output Q depends on the time relationship between the write clock and the read address signal.
The WIDTH (word length) and DEPTH (number of words) have continuous values but the choice of WIDTH limits the choice of DEPTH and vice versa.
The write enable (WE) and read enable (RE) signals are active high request signals for writing and reading, respectively; you may choose not to use them.