10.4.14 Synchronous/Asynchronous Dual Port RAM for ProASICPLUS®
This core provides dual-port RAM functionality supporting synchronous and asynchronous read and write operations.
Related Topics
Key Features
- Parameterized word length and depth
- Dual-port RAM architecture
- Asynchronous, synchronous-transparent or synchronous-pipelined read
- Asynchronous, or synchronous write
- Parity check or generate, both even and odd
- Supported netlist formats: EDIF, VHDL and Verilog
There is no limitation for depth and width. However, it is your responsibility to insure that the RAM’s used in a design can physically fit on the device chosen for the design.