10.4.5 Synchronous/Asynchronous Dual Port FIFO for ProASIC® and ProASIC®PLUS
This core has been obsoleted and must be used with caution.
See Implementation Rules .
Related Topics
Key Features
- Parameterized word length and depth
- Dual-port RAM architecture
- Asynchronous, synchronous-transparent or synchronous-pipelined read
- Asynchronous or synchronous write
- Parity check or generate, both even and odd
- Supported netlist formats: EDIF, VHDL and Verilog
There is no limitation for depth and width. However, it is your responsibility to ensure that the FIFOs used in a design can fit on the device chosen for the design.