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Libero IDE v9.x
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  2. 10 SmartGen Cores Reference
  3. 10.4 Memory and Controllers
  4. 10.4.3 Axcelerator FIFO
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    • 10.1 Basic Blocks
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    • 10.3 Fusion Peripherals
    • 10.4 Memory and Controllers
      • 10.4.1 Creating a RAM for IGLOO®, ProASIC® 3, SmartFusion® and Fusion
      • 10.4.2 FIFO Flag Controller (no RAM)
      • 10.4.3 Axcelerator FIFO
        • 10.4.3.1 Axcelerator FIFO Functionality
        • 10.4.3.2 Axcelerator FIFO I/O Description
        • 10.4.3.3 Axcelerator FIFO Parameter Description
        • 10.4.3.4 Axcelerator FIFO Implementation Rules
      • 10.4.4 Soft FIFO Controller
      • 10.4.5 Synchronous/Asynchronous Dual Port FIFO for ProASIC® and ProASIC®PLUS
      • 10.4.6 Synchronous Dual Port FIFO with Flags
      • 10.4.7 Synchronous Dual Port FIFO without Flags
      • 10.4.8 Synchronous FIFO for IGLOO®, ProASIC® 3, SmartFusion® and Fusion®
      • 10.4.9 FIFO Using Distributed Memory for ProASICPLUS®
      • 10.4.10 Axcelerator® RAM
      • 10.4.11 RAM Content Manager Summary
      • 10.4.12 Dual Port RAM for IGLOO®, ProASIC® 3 and Fusion®
      • 10.4.13 Synchronous/Asynchronous Dual Port RAM for DX/MX
      • 10.4.14 Synchronous/Asynchronous Dual Port RAM for ProASICPLUS®
      • 10.4.15 Two Port RAM
      • 10.4.16 RAM with Initialization
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10.4.3 Axcelerator FIFO

The Axcelerator FIFO is a configurable FIFO core that provides synchronous data buffering with programmable depth and status flags.

Related Topics

  • Axcelerator FIFO Functionality
  • Axcelerator FIFO I/O Description
  • Axcelerator FIFO Parameter Description
  • Axcelerator FIFO Implementation Rules

Key Features

  • Parameterized word length and FIFO depth
  • Dual-port synchronous FIFO
  • Active High/Low enable
  • Static/Programmable/No almost-empty and almost-full flags
  • Full and Empty flags
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  • Related Topics
  • Key Features

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