10.4.6 Synchronous Dual Port FIFO with Flags
The Synchronous Dual Port FIFO with Flags provides on-chip FIFO storage with programmable depth and status flag generation.
Supported Families
- eX
- SX-A
- SX
Related Topics
Key Features
- On-chip RAM
- Parameterized word length and depth
- FIFO full and empty flags
- Statically programmable almost-full flag
- Statically programmable almost-empty flag
- Global reset of the FIFO address pointers and flag logic
- Dual-port synchronous FIFO
Description
The Microchip FIFO cores use the 3200 DX and MX 32x8 or 64x4 dual-port RAM cells. Addresses are generated internally using counters and token chains to address the RAM. Dedicated read and write address data paths are used in the FIFO architecture. The read and write operations are totally independent and can be performed simultaneously.
The WIDTH (word length) and DEPTH (number of words) have continuous values but the choice of WIDTH limits the choice of DEPTH and vice versa.
The asynchronous clear signal, Aclr, can be active low or active high (low is the default option and should be used for all synchronous elements in the two supported families). When the asynchronous clear is active, all internal registers used to determine the current FIFO read and write addresses are reset to 0.
The FIFO is now in an empty state; the RAM content is not affected. When power is first applied to the FIFO, the FIFO must be initialized with an asynchronous clear cycle to reset the internal address pointers.
The full flag signal, FF, is optional and is available only for the High-Speed Flag (FFIFO) and the Medium-Speed Flag (MFFIFO) variations. The FF signal is active high only (if selected) and indicates when the FIFO is full.
The empty flag signal, EF, is optional and is available only for the High-Speed Flag (FFIFO) and the Medium-Speed Flag (MFFIFO) variations. The EF signal is active low only (if selected) and indicates when the FIFO is empty.
The write enable signals, WE and WEF and read enable signals, RE and REF, are active high requests for writing into and reading out of the FIFO respectively. The WE and RE signals control the logic associated with the FIFO write and read address pointers.
When WE is asserted high and FF is asserted low, a write cycle is initiated. When RE is asserted high and EF is asserted high, a read cycle is initiated. When RE and WE are asserted high at the same time, data are written into and read from the FIFO simultaneously.
The FIFO function offers a parameterizable almost-full flag (AFF). The AFF flag is asserted high when the FIFO contains AFF_VAL words or more.
The FIFO function offers a parameterizable almost-empty flag (AEF). The AEF flag is asserted low when the FIFO contains AEF_VAL words or less.