10.4.2 FIFO Flag Controller (no RAM)
The FIFO Flag Controller (no RAM) is designed for use with off-chip RAM and generates the flags typically used by a FIFO.
The following figure displays the FIFO Flag Controller (no RAM).

Supported Families
- 3200 DX
- MX
- SX
- SX-A
- eX
Description
The FIFO Flag Controller is designed for off-chip RAM. It is a state machine generating the flags typically used by a FIFO.
The asynchronous clear (Aclr) can be active low or active high (low is the default option and should be preferably used as for all synchronous elements in the two supported families). When the asynchronous clear is active, all internal registers are reset to '0'. The FIFO Controller is now in an empty state. At power up time, the FIFO must be initialized with an asynchronous clear cycle.
The full flag signal FF is optional. The FF signal is active high only (if selected) and indicates when the FIFO is full. The signal is asserted high on the rising (RISE) or falling (FALL) edge of the clock signal Clock with no delay. The FULL flag is always a function of the total block size not the user depth setting.
The empty flag signal EF is optional. The EF signal is active low only (if selected) and indicates when the FIFO is empty. The signal is asserted low on the rising (RISE) or falling (FALL) edge of the clock signal Clock with no delay.
The write enable (WE) and read enable (RE) signals are active high request signals for controlling the FIFO flags. They should be logically equivalent to the write and read enable controlling the off-chip RAM.
The FIFO Controller offers a parameterizable almost-full flag (AFF). AFF is asserted high when the FIFO contains AFF_VAL words or more. Otherwise, AFF is asserted low.
The FIFO Controller offers a parameterizable almost-empty flag (AEF). AEF is asserted low when the FIFO contains AEF_VAL words or less. Otherwise, AEF is asserted high.
Related Topics
Key Features
- Off-chip RAM
- Parameterized word length and depth
- FIFO full and empty flags
- Statically programmable almost-full flag to indicate when the FIFO core reaches a specific level
- Statically programmable almost-empty flag to indicate when the FIFO core reaches a specific level
- Global reset of the FIFO address pointers and flag logic
