10.4.6.3 Synchronous Dual Port Fifo with Flags Implementation Rules/Timing Diagrams

The following table lists the implementation rules for a Synchronous Dual Port Fifo with Flags.

Table 10-177. Timing Waveform Terminology
TermDescription
tckhlClock high/low period
trpReset pulse width
twesuWrite enable setup time
tresuRead enable setup time
tadsuData setup time
trcoData valid after clock high/low
tcoFlip-flop to clock output
traoData valid after read address has changed

The following figures illustrate the timing diagrams for a Synchronous Dual Port FIFO with Flags.

Figure 10-62. Reset Cycle
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Figure 10-63. Write and Read Cycle
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Figure 10-64. Full FIFO Timing Diagram
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Figure 10-65. Empty FIFO Timing Diagram
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Figure 10-66. Almost Full FIFO Timing Diagram
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