10.4.4.4 Soft FIFO Controller I/O Description
The following table lists the I/O description of a Soft FIFO Controller
| Name | Type | GENFILEParameter | Description |
|---|---|---|---|
| DATA | Input | DATA_IN_PN | The input data bus when writing the FIFO |
| Q | Output | DATA_OUT_PN | The output data bus when reading the FIFO |
| WE | Input | WE_PN | Write data into FIFO when signal is asserted |
| RE | Input | RE_PN | Read data from FIFO when signal is asserted |
| WCLOCK | Input | WCLOCK_PN | All signals in the write domain are synchronous to this clock |
| RCLOCK | Input | RCLOCK_PN | All signals in the read domain are synchronous to this clock |
| FULL | Output | FF_PN | Indicates that the FIFO is full |
| EMPTY | Output | EE_PN | Indicates that the FIFO is empty |
| RESET | Input | ACLR_PN | Asynchronous reset |
| AEMPTY | Output | AE_PN | Indicates that the FIFO has reached the Almost Empty threshold value |
| AFULL | Output | AF_PN | Indicates that the FIFO has reached the Almost Full threshold value |
| AEVAL | Output | AE_PORT_PN | Almost empty threshold value |
| AFVAL | Output | AF_PORT_PN | Almost full threshold value |
| WACK | Output | WACK_PN | Indicates that a write on the FIFO has succeeded |
| DVLD | Output | DVLD_PN | Indicates that a read on the FIFO has succeeded |
| OVERFLOW | Output | OVRFLOW_PN | Indicates that a write in the previous clock cycle failed |
| UNDERFLOW | Output | UDRFLOW_PN | Indicates that a read in the previous clock cycle has failed |
| RDCNT | Output | RDCNT_PN | The remaining number of elements in the FIFO from the read domain |
| WRCNT | Output | WRCNT_PN | The remaining number of elements in the FIFO from the write domain |
| CLOCK | Input | CLOCK_PN | Clock (in the case of single clock) |
| Name | Type | GENFILEParameter | Description |
|---|---|---|---|
| WE | Input | WE_PN | Write data into FIFO when signal is asserted |
| RE | Input | RE_PN | Read data from FIFO when signal is asserted |
| WCLOCK | Input | WCLOCK_PN | All signals in the write domain are synchronous to this clock |
| RCLOCK | Input | RCLOCK_PN | All signals in the read domain are synchronous to this clock |
| FULL | Output | FF_PN | Indicates that the FIFO is full |
| EMPTY | Output | EE_PN | Indicates that the FIFO is empty |
| RESET | Input | ACLR_PN | Asynchronous reset |
| AEMPTY | Output | AE_PN | Indicates that the FIFO has reached the Almost Empty threshold value |
| AFULL | Output | AF_PN | Indicates that the FIFO has reached the Almost Full threshold value |
| AEVAL | Output | AE_PORT_PN | Almost empty threshold value |
| AFVAL | Output | AF_PORT_PN | Almost full threshold value |
| WACK | Output | WACK_PN | Indicates that a write on the FIFO succeeded |
| DVLD | Output | DVLD_PN | Indicates that a read on the FIFO succeeded |
| OVERFLOW | Output | OVRFLOW_PN | Indicates that a write in the previous clock cycle failed |
| UNDERFLOW | Output | UDRFLOW_PN | Indicates that a read in the previous clock cycle has failed |
| RDCNT | Output | RDCNT_PN | The remaining number of READ domain elements in the FIFO |
| WRCNT | Output | WRCNT_PN | The remaining number of WRITE domain elements in the FIFO |
| MEMWADDR | Output | MEMWADDR_PN | Memory write address for external memory |
| MEMRADDR | Output | MEMRADDR_PN | Memory read address for external memory |
| MEMWE | Output | MEMWE_PN | Memory write enable for external memory |
| MEMRE | Output | MEMRE_PN | Memory read enable for external memory |
| CLOCK | Input | CLOCK_PN | Clock |