10.4.5.1 Synchronous/Asynchronous Dual Port FIFO for ProASIC® and ProASIC®PLUS I/O Description
This core has been obsoleted and must be used with caution.
See the Implementation Rules.
The following figure shows the I/O interface of the Synchronous/Asynchronous Dual Port FIFO for ProASIC and ProASICPLUS.
The following table lists the I/O ports of the Synchronous/Asynchronous Dual Port FIFO for ProASIC and ProASICPLUS.
| Port Name | Size | Type | Required/Optional | Function |
|---|---|---|---|---|
| DI<0:8> | 9 | Input | Required | Input data bits <0:8>; <8> can be used for parity IN |
| LEVEL | 8A | Input | Optional | Defines when EQTH and GEQTH should react (hardcoded for static trigger level) |
| WRB | 1 | Input | Required | Write pulse (active low) |
| RDB | 1 | Input | Required | Read pluse (active low) |
| WCLK | 1 | Input | Required | Write clock (active high) |
| RCLK | 1 | Input | Required | Read clock (active low) |
| RESET | 1 | Input | Required | Reset for FIFO pointers (active low) |
| DO<0:8> | 9 | Output | Required | Output data bits <0:8>; <8> can be used for parity OUT |
| EMPTY | 1 | Output | Required | Empty flag |
| FULL | 1 | Output | Required | Full flag |
| EQTH | 1 | Output | Required | Flag is true when FIFO hold (LEVEL) words |
| GEQTH | 1 | Output | Required | Flag is true when FIFO hold (LEVEL) words or more |
| PI | WIDTH | Input | Optional | Input parity bits |
| PO | log2(width) | Output | Optional | Parity bits |
| WPE | 1 | Output | Optional | Write parity error flag (active HIGH), available only for parity checking models |
| RPE | 1 | Output | Optional | Read parity error flag (active HIGH), available only for parity checking models |
| PARODD | 1 | Input | Optional | Selects ODD parity generation/detect when HIGH; selects EVEN parity when LOW |
A. LEVEL is always eight bits. That means for values of DEPTH greater than 256 not all values are possible, for example, for DEPTH =512, LEVEL can have the values 2, 4, … , 512.
This holds true only for dynamically triggered FIFOs. For a static trigger, all values of the depth are possible. In the case of dynamic trigger, only values that are divisible by the number of 256X9 FIFO blocks cascaded to achieve the required depth are possible.
In simulation, EQTH/GEQTH reacts to LEVEL * [# of 256x9 modules (rounded up)].
For example, with 1000x32 sync dynamic, level=1, EQTH/GEQTH toggles after 4 reads. For a 700x32 sync dynamic, level=1, EQTH/GEQTH toggles after 3 reads.