10.4.5.2 Synchronous/Asynchronous Dual Port FIFO for ProASIC® and ProASIC®PLUS Parameter Description
This core has been obsoleted and must be used with caution.
The following tables list the parameter and implementation settings of the Synchronous/Asynchronous Dual Port FIFO for ProASIC and ProASICPLUS.
| Parameter | Value | Function |
|---|---|---|
| WIDTH | Width | Word length of DI and DO |
| DEPTH | Depth | Number of RAM words |
| RDA | Async transparentPipelined | Read data access |
| WRA | async sync | Write data access |
| Optional | speed area | Optimization |
| PARITY | checkeven checkoddgeneven genodd none | Parity check or parity generation |
| Parameter | Value | Description |
|---|---|---|
| LPMTYPE | LPM_FIFO_DQ | Generic FIFO category |
| LPM_HINT | FIFO_DYN | FIFO with dynamic trigger level |
| FIFO_STATIC | FIFO with static trigger level |