10.4.14.1 Synchronous/Asynchronous Dual Port RAM for ProASICPLUS® I/O Description

The following figure shows the I/O interface of the Synchronous/Asynchronous Dual Port RAM for ProASICPLUS.

The following table lists the I/O ports of the Synchronous/Asynchronous Dual Port RAM and ProASICPLUS.

Table 10-200. I/O Description
Port Name	Size	Type	Required/Optional	Function
DI	WIDTH	Input	Required	Input Data
RADDR	log2 (DEPTH)	Input	Required	Read Address
WADDR	log2 (DEPTH)	Input	Required	Write Address
WRB	1	Input	Required	Write pulse (active low )
DIS	1	Input	Optional	DMUX select; please refer to the Deep Memories section of the ProASICPLUS RAM/FIFO blocks application note
RDB	1	Input	Required	Read pulse (active low )
WCLK	1	Input	Required	Write Clock (active high)
RCLK	1	Input	Required	Read Clock (active high)
DO	WIDTH	Output	Required	Output data
DOS	1	Output	Optional	DMUX select; please refer to the Deep Memories section of the ProASICPLUS RAM/FIFO blocks application note
PI	WIDTH	Input	Optional	Input parity bits
PO	log2(WIDTH)	Output	Optional	Parity bits
WPE	1	Output	Optional	Write parity error flag
RPE	1	Output	Optional	Read parity error flag