2.2.16 Simulate Pre/Post Synthesis

FlashROM uses the MEM file for simulation. The MEM file contains 128 rows of 8‑bit values, representing the contents of FlashROM. Any unspecified FlashROM locations default to 0.

During simulation, use the MEM file together with the design netlist and testbench. The VITAL and Verilog simulation models accept the generics passed by the netlist, read the MEM file, and simulate the design using the data contained in the file.

In addition to using the generated MEM file, you may create a binary file with 128 rows of 8‑bit values and save it as a MEM file. If multiple MEM files are used, it is recommended that each file have a unique name.

During place‑and‑route in Designer, the software recognizes the MEM‑file reference passed through the netlist generics and propagates the MEM file link to the output netlist.

If you are using Libero IDE, use the synthesis tools to synthesize your design. Libero generates post‑synthesis files that can be used for simulation. Use your synthesis tool to generate the corresponding EDIF netlist.