28.1.3 Deadman Timer Clear Register
Note:
- Bits 7:0 are cleared when the DMT Counter is reset by writing a correct sequence of STEP1 and STEP2.
| Name: | DMTCLR |
| Offset: | 0x064 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STEP2[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – STEP2[7:0] DMT Clear Timer bits
| Value | Description |
|---|---|
| 00001000 | Clears STEP1[7:0], STEP2[7:0] and the Deadman Timer if preceded by the correct loading of the STEP1[7:0] bits in the correct sequence. The write to these bits may be verified by reading the DMTCNTL/H registers and observing the counter being reset. |
| All Other Write Patterns | Sets the BAD2 bit; the value of STEP1[7:0] will remain unchanged and the new value being written to STEP2[7:0] will be captured(1). |