28.1.7 DMT Hold Register
Note:
- The DMTHOLDREG register is initialized to ‘
0’ on Reset, and is only loaded when the DMTCNTL andDMTCNTH registers are read.
| Name: | HOLDREG(1) |
| Offset: | 0x070 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| UPRCNT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UPRCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |