3.10.6.5.12 DBGSW – Debug Support Switch


Bit	7	6	5	4	3	2	1	0
	DBGSE	CPBF	CPBFOS[1:0]		DBGGS[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – DBGSE Debug Support Switch Enable

The debug support switch enable bit enables the debug support test mode. The selected signal group (DBGGS) overrides the normal port functionality.

The Data Direction Register (DDR) bit which corresponds to the debugging support pins (PC1, PC3, PC4, PC5, PB0, PB4) must be set in order to enable the output driver.

Bit 6 – CPBF CPU Busy Flag

This bit indicates that the CPU is busy. It will be automatically set if an interrupt is executed or if software writes the bit to ‘1’. It will be cleared if software writes the bit to ‘0’.

Bits 5:4 – CPBFOS[1:0] CPU Busy Flag Output Select

Selects the output port for the CPBF bit state. The selected port overrides the normal port functionality including the data direction register.


CPBFOS[1]	CPBFOS[0]	Selected Output Port
`0`	`0`	No output port selected
`0`	`1`	PB0
`1`	`0`	PB4
`1`	`1`	PC1

Bits 3:0 – DBGGS[3:0] Debugging Support Group Select

The four debug support group select bits code the group of internal signals, which are routed to the respective output pins.


DBGGS[3:0]	PC1	PC3	PC4	PC5	PB0	PB4
0	WCOB	WCOA	SOTB	SOTA	EOTB	EOTA
1	WCOB	SOTB	EOTB	NBITB	`0`	`0`
2	WCOA	SOTA	EOTA	NBITA	`0`	`0`
3	0	SSMERR	SSMESM3	SSMESM2	SSMESM1	SSMESM0
4	SFIDOA	WUPOA	MANOA	SYTOA	AMPOA	CAROA
5	SFIDOB	WUPOB	MANOB	SYTOB	AMPOB	CAROB
6	MANFB	SYTFB	AMPFB	CARFB	`0`	`0`
7	MANFA	SYTFA	AMPFA	CARFA	`0`	`0`
8	GPIOR0[5]	GPIOR0[4]	GPIOR0[3]	GPIOR0[2]	GPIOR0[1]	GPIOR0[0]
9	GPIOR3[5]	GPIOR3[4]	GPIOR3[3]	GPIOR3[2]	GPIOR3[1]	GPIOR3[0]
10	GPIOR4[7]	GPIOR4[6]	GPIOR4[5]	GPIOR4[4]	GPIOR4[3]	GPIOR4[2]
11	GPIOR5[5]	GPIOR5[4]	GPIOR5[3]	GPIOR5[2]	GPIOR5[1]	GPIOR5[0]
12	GPIOR6[5]	GPIOR6[4]	GPIOR6[3]	GPIOR6[2]	GPIOR6[1]	GPIOR6[0]
13	0	SSMST4	SSMST3	SSMST2	SSMST1	SSMST0
14	SSMSTA5	SSMSTA4	SSMSTA3	SSMSTA2	SSMSTA1	SSMSTA0
15	SSMSTB5	SSMSTB4	SSMSTB3	SSMSTB2	SSMSTB1	SSMSTB0

Name:	DBGSW
Offset:	0x156
Reset:	0x00