3.10.6.5.8 DBCR – Debounce Control Register

Name:	DBCR
Offset:	0x152
Reset:	0x00

Changes to the DBCR register are only allowed when debouncing is disabled (set all DBENx registers to 0x00)


Bit	7	6	5	4	3	2	1	0
					DBHA	DBTMS	DBCS	DBMD
Access	R	R	R	R	R	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 6 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 5 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 4 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 3 – DBHA Debounce Handshake Active Flag

This flag is set to ‘1’ while the debounce handshake is active. The DBHA flag must be ‘0’ before the I/O-clock is disabled (for example, going to sleep mode other than “idle”). Debouncing does not continue if the handshake of a previous event is not finished.

Bit 2 – DBTMS Debounce Timer Mask Select

The 8-bit debounce timer compare register DBTC is compared with the 15-bit timer value. The range of the comparison between the 8-bit DBTC and the 15-bit timer value is selected by the DBTMS bit, as shown in the following table. The resulting debounce timings are shown in Table 3-86.

Table 3-83. Debounce Timer Compare Mask Select
DBTMS	Comparison Range	Application Example
`0`	Bit 14 – Bit 7	Key debouncing
`1`	Bit 7 – Bit 0	LIN-Bus debouncing

Bit 1 – DBCS Debounce Clock Select

The debounce clock select bit selects the source clock of the debounce block, see the following table.

Table 3-84. Debounce Clock Select
DBCS	Clock Source	Application Example
`0`	CLK_SRC(f_typ= 125kHz)	Key debouncing
`1`	CLK_FRC(f_typ= 6.36MHz)	LIN-Bus debouncing

Bit 0 – DBMD Debounce Mode

This bit selects the common mode for port debouncing. If this bit is cleared (DBMD = 0), debounce mode 0 (stable mode) is active (see Debounce Stable Mode). If this bit is set (DBMD = 1), debounce mode 1 (fast mode) is active (see Debounce Fast Mode).