3.10.7.2.1.3 T1COR – Timer1
Compare Register
| Name: | T1COR |
| Offset: | 0x070 |
| Reset: | 0x00 |
The compare
register contains an 8-bit value that is continuously compared with the counter value
(T1CNT). A match can be used to generate a compare interrupt, a counter reset or an
output clock CLKT1. The compare register can be written while the timer is
running. Potential compare match interrupts generated from glitches on the clock domain
crossing are ignored for two AVR clock cycles.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | T1COR[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – T1COR[7:0] Timer1 Counter
Compare Value
