3.10.7.2.1.4 T1IFR – Timer1 Interrupt Flag Register


Bit	7	6	5	4	3	2	1	0
							T1COF	T1OFF
Access	R	R	R	R	R	R	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 6 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 5 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 4 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 3 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 2 – Reserved Bit

This bit is reserved and read as ‘0’.

Bit 1 – T1COF Timer1 Compare Flag

This flag is set to ‘1’ during the clock cycle after the counter value has matched with the compare register. The flag (T1COF) is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical ‘1’ to it.

Bit 0 – T1OFF Timer1 Overflow Flag

This flag is set by the T1OVF signal when the counter reaches its maximum value (0xFF). If the I bit in SREG and the T1OIM bit are set in T1IMR, the MCU jumps to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical ‘1’ to it.

Note: The overflow flag is also set if the compare value is set to FF.

Name:	T1IFR
Offset:	0x015
Reset:	0x00