3.10.7.2.1.1 T1CR – Timer1 Control Register

Name: T1CR
Offset: 0x011
Reset: 0x00

Bit 76543210 
 T1ENAT1TOST1REST1TOPT1CRMT1CTMT1OTM 
Access R/WR/WWR/WRR/WR/WR/W 
Reset 00000000 

Bit 7 – T1ENA Timer1 Enable

This bit controls the Timer1 block. The T1ENA bit must be written to logic ‘1’ to enable Timer1. If the T1ENA bit is written to logic ‘0’, Timer1 is disabled. Reading this bit shows the actual state of Timer1. Because internal synchronization requires 2½ asynchronous CL1 clock cycles to enable or disable Timer1, it may take some time to read a logic ‘1’ after having enabled Timer1. The same applies for disabling.

Care has to be taken if the T1ENA or T1CR register is written by consecutive cbi/sbi instructions. For example, clearing the T1ENA bit with a cbi instruction followed by a cbi/sbi instruction on another bit of the T1CR re-enables the timer. (The read-modify-write sequence is still reading the T1ENA = 1 and writing it back, thus, enabling the timer).

The asynchronous clock can be forced on without synchronization by writing a logic ‘1’ to the T1ENA bit twice within four AVR clock cycles. This can be useful for slow clocks, for example, when the first edge of a newly enabled oscillator leads to an increased counter value.

Bit 6 – T1TOS Timer1 Toggle with Start

The T1TOS bit must be written to logic ‘1’ if the modulator output of Timer1 must be toggled when the timer is enabled with T1ENA. If the T1TOS bit is written to logic ‘0’, the modulator output of Timer1 is not toggled with the timer enables.

Bit 5 – T1RES Timer1 Reset

The T1RES bit can be written to logic ‘1’ to reset the prescaler and counter. This is only allowed if the timer is stopped (T1ENA = 0). The T1RES bit is automatically cleared one cycle after the write.

Bit 4 – T1TOP Timer1 Toggle Output Preset

The T1TOP bit must be written to logic ‘1’ to set the toggle flip-flop. Clearing the T1TOP resets the toggle flip-flop. This bit allows the programmer to preset the toggle output flip-flop in the modulator of Timer1. If the timer is stopped, this bit shows the actual value of the toggle flip-flop.
Note: If T1ENA = 1, no output preset is possible.

Bit 3 –  Reserved Bit

This bit is reserved and reads as ‘0’.

Bit 2 – T1CRM Timer1 Compare Reset Mask

The T1CRM bit must be written to logic ‘1’ to enable the counter reset if a match of the counter with the compare register occurs. If the T1CRM bit is written to logic ‘0’, the counter reset is disabled.

Bit 1 – T1CTM Timer1 Compare Toggle Mask

The T1CTM bit must be written to logic ‘1’ to enable the compare toggle. If the T1CTM bit is written to logic ‘0’, the compare toggle is disabled. A match of the counter with the compare register generates an output clock of the counter (CLKT1).

Bit 0 – T1OTM Timer1 Overflow Toggle Mask

The T1OTM bit must be written to logic ‘1’ to enable the overflow toggle. If the T1OTM bit is written to logic ‘0’, the overflow toggle is disabled. A counter overflow generates an output clock of the counter (CLKT1).