3.10.7.2.1.5 T1IMR – Timer1
Interrupt Mask Register
| Name: | T1IMR |
| Offset: | 0x072 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | T1CIM | T1OIM | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 1 – T1CIM Timer1 Compare Interrupt Mask
If the T1CIM bit is written to
‘1’ and the I bit in SREG is set, the Timer1 compare match
interrupt is enabled. The corresponding interrupt is executed if a compare match
occurs, i.e., when the T1COF bit is set in the Timer1 interrupt flag register
(T1IFR).
Bit 0 – T1OIM Timer1 Overflow Interrupt Mask
If the T1OIM bit is written to
‘1’ and the I bit in SREG is set, the Timer1 overflow interrupt
is enabled. The corresponding interrupt is executed if a counter overflow occurs,
i.e., when the T1OFF bit is set in the Timer1 interrupt flag register
(T1IFR).
