3.10.7.6.1.2 T5IFR – Timer5
Interrupt Flag Register
| Name: | T5IFR |
| Offset: | 0x019 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | T5COF | T5OFF | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – T5COF Timer5 Output
Compare Match Flag
This flag is set in the timer
clock cycle after the counter (T5CNT) value matches the output compare register
(T5OCR). T5COF is automatically cleared when the output compare match interrupt
vector is executed. Alternatively, T5COF can be cleared by writing a logic
‘1’ to its bit location.
Bit 0 – T5OFF Timer5 Overflow
Flag
T5OFF flag is set when the
timer overflows. T5OFF is automatically cleared when the Timer5 overflow interrupt
vector is executed. Alternatively, T5OFF can be cleared by writing a logic
‘1’ to its bit location.
