3.10.7.6.1.8 GTCCR – General
Timer/Counter Control Register
| Name: | GTCCR |
| Offset: | 0x090 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | TSM | | | | | | | PSR10 | |
| Access | R/W | R | R | R | R | R | R | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – TSM Timer
Synchronization Mode
Writing the TSM bit to
‘1’ activates the timer synchronization mode. In this mode, the
value that is written to the PSR10 bit is retained and thus keeps the corresponding
prescaler reset signals asserted. This ensures that the corresponding timers are
stopped and can be configured to the same value without the risk of one of them
advancing during configuration. When the TSM bit is written to ‘0’,
the PSR10 bit is cleared by hardware and the timers start counting
simultaneously.
Bit 6 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 0 – PSR10 Prescaler
Reset
When this bit is
‘1’, the Timer5 prescaler is reset. This bit is normally
cleared immediately by hardware, unless the TSM bit is set.
