The T5CNTH/L registers
provide direct access, both for read and for write operations to the 16-bit counter. The
T5CNTL register represents the lower byte of the counter value. To ensure that both the
high and low bytes are read and written simultaneously when the CPU accesses these
registers, the access is performed using an 8-bit temporary high-byte register (TEMP).
This temporary register is shared by all the other 16-bit registers.
See Accessing 16-bit Registers section for more details. Modifying T5CNTL while the counter is running processes
poses the risk of missing a compare match between T5CNT and the T5OCR register.
Writing to the T5CNTL register blocks (removes) the compare match on the following
timer clock.
Name:
T5CNTL
Offset:
0x08D
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
T5CNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 7:0 – T5CNT[7:0] Timer5 Counter
Value Low Byte
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