13.16.3 V_REG Low-Dropout (LDO) Linear Regulator

The 3.3V VREG LDO is used for internal gate control logic and can also be used to power the host dsPIC DSC.

The VREG LDO is capable of supplying 70 mA of external load current. The regulator has a minimum overcurrent limit of 80 mA. When the regulator current exceeds the overcurrent limit, the regulator will enter a True Current and Voltage Foldback mode based upon load impedance. As the load impedance decreases towards zero ohms, the regulator output current and voltage will also decrease until the final foldback current and voltage are attained.

When the regulator output voltage drops below the VR_EG undervoltage limit, the VREGUVF Undervoltage Fault bit will be set in the STAT1 register. The regulator will remain active during the Fault. Table 13-2 shows the registers and bits associated with Faults.

The V_REG LDO will be disabled when the HV_DD supply voltage Undervoltage Fault occurs. The V_REG LDO will be re-enabled when the conditions in Voltage Supervisor are met.

A minimum of 4.7 µF ceramic output capacitance is required for the V_REG LDO; 10 µF is recommended to increase transient performance if supplying the host dsPIC DSC.

The V_REG LDO is disabled while the system is in Sleep mode.