13.4.45 ADC Early Interrupt Status Register High(1)
Note:
- Bit availability is dependent on the number of supported ADC channels. Refer to dsPIC33CK512MP608 Product Families for ADC channel availability on package variants.
| Name: | ADEISTATH |
| Offset: | 0xBFA |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EISTAT[27:24] | |||||||||
| Access | HS/R | HS/R | HS/R | HS/R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EISTAT[23:16] | |||||||||
| Access | HS/R | HS/R | HS/R | HS/R | HS/R | HS/R | HS/R | HS/R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 11:0 – EISTAT[27:16] Early Interrupt Status for Corresponding Analog Input bits
| Value | Description |
|---|---|
1 |
Early interrupt was generated |
0 |
Early interrupt was not generated since the last ADCBUFx read |