13.4.15 ADC Data Ready Status Register Low(1)
Note:
- Bit availability is dependent on the number of supported ADC channels. Refer to dsPIC33CK512MP608 Product Families for ADC channel availability on package variants.
Legend: HSC = Hardware Settable/Clearable bit
| Name: | ADSTATL |
| Offset: | 0xB30 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| AN[15:0]RDY | |||||||||
| Access | HSC/R | HSC/R | HSC/R | HSC/R | HSC/R | HSC/R | HSC/R | HSC/R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| AN[15:0]RDY | |||||||||
| Access | HSC/R | HSC/R | HSC/R | HSC/R | HSC/R | HSC/R | HSC/R | HSC/R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – AN[15:0]RDY Data Ready Status for Corresponding Analog Input bits
| Value | Description |
|---|---|
1 |
Channel conversion result is ready in the corresponding ADCBUFx register |
0 |
Channel conversion result is not ready |