LAN8670/1/2

Description
Conformity
1 Preface
2 Introduction
3 Pin Description and Configuration
4 Functional Descriptions
5 Register Descriptions
- 5.1 SMI Basic Control and Status Registers
- 5.2 PMA/PMD Registers
- 5.3 PCS Registers
- 5.4 Miscellaneous Registers
  - 5.4.1 Configuration Protection Control
    Configuration Protection Control
  - 5.4.2 Control 1 Register
    Control 1 Register
  - 5.4.3 Pin Control Register
    Pin Control Register
  - 5.4.4 Status 1 Register
    Status 1 Register
  - 5.4.5 Status 2 Register
    Status 2 Register
  - 5.4.6 Status 3 Register
    Status 3 Register
  - 5.4.7 Interrupt Mask 1 Register
    Interrupt Mask 1 Register
  - 5.4.8 Interrupt Mask 2 Register
    Interrupt Mask 2 Register
  - 5.4.9 Counter Control Register
    Counter Control Register
  - 5.4.10 Transmit Opportunity Count (High)
    Transmit Opportunity Count (High)
  - 5.4.11 Transmit Opportunity Count (Low)
    Transmit Opportunity Count (Low)
  - 5.4.12 BEACON Count (High)
    BEACON Count (High)
  - 5.4.13 BEACON Count (Low)
    BEACON Count (Low)
  - 5.4.14 PLCA Multiple ID 0 Register
    PLCA Multiple ID 0 Register
  - 5.4.15 PLCA Multiple ID 1 Register
    PLCA Multiple ID 1 Register
  - 5.4.16 PLCA Multiple ID 2 Register
    PLCA Multiple ID 2 Register
  - 5.4.17 PLCA Multiple ID 3 Register
    PLCA Multiple ID 3 Register
  - 5.4.18 Port Management 2
    Port Management 2
  - 5.4.19 Inactivity Watchdog Timeout (High)
    Inactivity Watchdog Timeout (High)
  - 5.4.20 Inactivity Watchdog Timeout (Low)
    Inactivity Watchdog Timeout (Low)
  - 5.4.21 Transmit Match Control Register
    Transmit Match Control Register
  - 5.4.22 Transmit Match Pattern (High) Register
    Transmit Match Pattern (High) Register
  - 5.4.23 Transmit Match Pattern (Low) Register
    Transmit Match Pattern (Low) Register
  - 5.4.24 Transmit Matched Packet Delay Register
    Transmit Matched Packet Delay Register
  - 5.4.25 Receive Match Control Register
    Receive Match Control Register
  - 5.4.26 Receive Match Pattern (High) Register
    Receive Match Pattern (High) Register
  - 5.4.27 Receive Match Pattern (Low) Register
    Receive Match Pattern (Low) Register
  - 5.4.28 Receive Matched Packet Delay Register
    Receive Matched Packet Delay Register
  - 5.4.29 Credit Based Shaper Stop Threshold (High) Register
    Credit Based Shaper Stop Threshold (High) Register
  - 5.4.30 Credit Based Shaper Stop Threshold (Low) Register
    Credit Based Shaper Stop Threshold (Low) Register
  - 5.4.31 Credit Based Shaper Start Threshold (High) Register
    Credit Based Shaper Start Threshold (High) Register
  - 5.4.32 Credit Based Shaper Start Threshold (Low) Register
    Credit Based Shaper Start Threshold (Low) Register
  - 5.4.33 Credit Based Shaper Slope Control Register
    Credit Based Shaper Slope Control Register
  - 5.4.34 Credit Based Shaper Top Limit (High) Register
    Credit Based Shaper Top Limit (High) Register
  - 5.4.35 Credit Based Shaper Top Limit (Low) Register
    Credit Based Shaper Top Limit (Low) Register
  - 5.4.36 Credit Based Shaper Bottom Limit (High) Register
    Credit Based Shaper Bottom Limit (High) Register
  - 5.4.37 Credit Based Shaper Bottom Limit (Low) Register
    Credit Based Shaper Bottom Limit (Low) Register
  - 5.4.38 Credit Based Shaper Credit Counter (High) Register
    Credit Based Shaper Credit Counter (High) Register
  - 5.4.39 Credit Based Shaper Credit Counter (Low) Register
    Credit Based Shaper Credit Counter (Low) Register
  - 5.4.40 Credit Based Shaper Control Register
    Credit Based Shaper Control Register
  - 5.4.41 PLCA Skip Control Register
    PLCA Skip Control Register
  - 5.4.42 PLCA Transmit Opportunity Skip Register
    PLCA Transmit Opportunity Skip Register
  - 5.4.43 Application Controlled Media Access Control Register
    Application Controlled Media Access Control Register
  - 5.4.44 Sleep Control 0 Register
    Sleep Control 0 Register
  - 5.4.45 Sleep Control 1 Register
    Sleep Control 1 Register
  - 5.4.46 Collision Detector Control 0 Register
    Collision Detector Control 0 Register
  - 5.4.47 SQI Control Register
    SQI Control Register
  - 5.4.48 SQI Status 0 Register
    SQI Status 0 Register
  - 5.4.49 SQI Configuration 0 Register
    SQI Configuration 0 Register
  - 5.4.50 SQI Configuration 2 Register
    SQI Configuration 2 Register
  - 5.4.51 Pad Control 3 Register
    Pad Control 3 Register
  - 5.4.52 Analog Control 5
    Analog Control 5
  - 5.4.53 OPEN Alliance Map ID and Version Register
    OPEN Alliance Map ID and Version Register
  - 5.4.54 PLCA Control 0 Register
    PLCA Control 0 Register
  - 5.4.55 PLCA Control 1 Register
    PLCA Control 1 Register
  - 5.4.56 PLCA Status Register
    PLCA Status Register
  - 5.4.57 PLCA Transmit Opportunity Timer Register
    PLCA Transmit Opportunity Timer Register
  - 5.4.58 PLCA Burst Mode Register
    PLCA Burst Mode Register
6 Application Information
7 Operational Characteristics
8 Packaging Information
9 Package Marking Information
Product Identification System
Data Sheet Revision History
Microchip Information

5.4.47 SQI Control Register

Name:	SQICTL
Address:	0x00A0


Bit	15	14	13	12	11	10	9	8
	SQIRST	SQIEN
Access	R/W SC	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	1	0	1	0	0


Bit	7	6	5	4	3	2	1	0

Access	R/W	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0

Bit 15 – SQIRST SQI Reset

Setting this bit will reset the SQI block. This bit is self-clearing.

Value	Description
`0`	Normal Operation
`1`	SQI block is reset

Bit 14 – SQIEN SQI Enable

This bit enables the SQI measurement process when set.

Value	Description
`0`	SQI is disabled
`1`	SQI is enabled

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.