5.4.54 PLCA Control 0 Register
| Name: | PLCA_CTRL0 |
| Address: | 0xCA01 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EN | RST | ||||||||
| Access | R/W | R/W SC | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 – EN PLCA Enable
Setting this bit will enable Physical Layer Collision Avoidance. When this bit is clear, the PHY will operate in pure CSMA/CD mode.
Note: When PLCA is enabled on a properly configured mixing
segment, no collisions should occur on the physical layer. It is therefore
recommended to disable physical layer collision detection to achieve a higher level
of noise tolerance.
| Value | Description |
|---|---|
0 |
The PLCA reconciliation sublayer is disabled and the PHY operates in normal CSMA/CD mode without the performance enhancements of PLCA. |
1 |
The Physical Layer Collision Avoidance (PLCA) reconciliation sublayer functionality is enabled. |
Bit 14 – RST PLCA Reset
Writing ‘1’ to this bit will result in a reset of the PLCA reconciliation sublayer.
Note: This bit is self-clearing. When
setting this bit, do not set other bits in this register.
| Value | Description |
|---|---|
0 |
Normal operation |
1 |
PLCA reconciliation sublayer is reset |