5.4.2 Control 1 Register
| Name: | CTRL1 |
| Address: | 0x0010 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IWDE | BCAEN | DIGLBE | |||||||
| Access | RO | RO | RO | RO | R/W | R/W | R/W | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - |
Bit 3 – IWDE Inactivity Watchdog Enable
When set, this bit enables the (MII/SC-MII/RMII/SMI) inactivity watchdog.
| Value | Description |
|---|---|
0 |
Inactivity watchdog disabled |
1 |
Inactivity watchdog enabled |
Bit 2 – BCAEN Broadcast Address Enable
When set, this the PHY will respond to SMI address 0x00 in addition to the address configured by the PHYADn configuration straps.
| Value | Description |
|---|---|
0 |
PHY will ignore SMI accesses to address 0x00. |
1 |
PHY will respond to SMI accesses to address 0x00. |
Bit 1 – DIGLBE Digital Loopback Enable
Enables a digital loopback from the differential Manchester encoder to the decoder.
| Value | Description |
|---|---|
0 |
Normal operation |
1 |
Digital loopback enabled |