43.4 Power Supply DC Module Electrical Specifications

Table 43-5. Power Supply DC Electrical Specifications
AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V (unless otherwise stated)

Operating Temperature: -40°C ≤ TA ≤ +85°C for Industrial Temp

-40°C ≤ TA ≤ +125°C for Extended Temp
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
REG_1 VDDCORE_CIN

VDDCORE (CLDO_OUT) input bypass parallel capacitor pair(5)

 — 1 — µF Bulk ceramic or solid tantalum with ESR <0.5Ω. Min and max represent absolute values including cap tolerances
— 100 — nF Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_5 VDD33

VDD33 input bypass parallel capacitor pair(5)

 — 10 — μF Bulk ceramic or solid tantalum with ESR <0.5Ω(5)
— 100 — nF Ceramic XR7/X5R with ESR <0.5Ω depending on temperature on all VDDIO pins(5)
REG_6 PMU_VDDIO Input bypass parallel capacitor pair for the PMU power section(5) — 4.7 — μF Bulk Ceramic or solid Tantalum with ESR <0.5Ω(5)
REG_7 PMU_VDDP Input bypass parallel capacitor pair for the PMU power section(5) — 1 — μF Bulk ceramic or solid tantalum with ESR <0.5Ω(5)
REG_9 VDDFLASH_CIN VDD_FLASH bypass parallel capacitor pair(5) — 10 — μF Bulk ceramic or solid tantalum with ESR <0.5Ω(5)
— 100 — nF Ceramic XR7/X5R with ESR <0.5Ω depending on temperature on all VDDFLASH pins(5)
REG_17 VDDANA_CIN VDDANA input bypass parallel capacitor pair(5) — 10 — μF Bulk ceramic or solid tantalum with ESR <0.5Ω(5)
— 0.1 — nF Ceramic XR7/X5R with ESR <0.5Ω
REG_18 VDDANA_LEXT VDDANA series ferrite bead DCR (DC resistance) — — 0.1 Ω ≥600Ω at 100 MHz
REG_19 Ferrite bead current Rating(1) 100 — — mA —
REG_20 BUCK_PLL_CIN VDD bypass capacitor on the BUCK_PLL input — 1 — μF Ceramic XR7/X5R with ESR <0.5Ω
REG_21 BUCK_BB_CIN VDD bypass capacitor on the BUCK_BB input — 1 — μF Ceramic XR7 with ESR <0.5Ω
REG_22 BUCK_MPA_CIN VDD bypass capacitor on the BUCK_LPA input — 1 — μF Ceramic XR7 with ESR <0.5Ω
REG_23 BUCK_LPA_CIN VDD bypass capacitor on the BUCK_MPA input — 1 — μF Ceramic XR7 with ESR <0.5Ω
REG_24 BUCK_CLDO_CIN VDD bypass capacitor on the BUCK_CLDO input — 1 — μF Ceramic XR7 with ESR <0.5Ω
REG_25 R_EXT Bias for reference current generation — 30 — kΩ —
REG_27 VSW_LEXT(2,3) Buck Switch mode regulator inductor inductance — 4.7 — μH Shielded inductor only
REG_29 Inductor DCR (DC resistance) — — 0.22 Ω —
REG_31 Inductor ISAT rating(2,6) 250 — — mA —
REG_32 VSW_CAPEXT Buck Switch mode regulator bulk capacitor capacitance 10 — — μF —
REG_32A Buck Switch mode regulator filtering capacitor capacitance 100 — — nF —
REG_36 VDDCORE VDDCORE voltage range 1.14 1.2 1.26 V MCU Active, cache and prefetch disabled while executing from Flash
REG_37 VDD33(4) VDD33 input voltage range 1.9 3.3 3.6 V —
REG_39 VDDANA(4) VDDANA input voltage range 1.9 3.3 3.6 V —
REG_40 VDD_PMU PMU output voltage 1.30 1.35 1.40 V PMU output voltage
REG_43 SVDDIO_R

VDDIO rise ramp rate to ensure internal Power-on Reset signal

 0.03 — 0.11 V/ms Failure to meet this specification may lead to start-up or unexpected behaviors
REG_44 SVDDIO_F VDDIO falling ramp rate to ensure internal Power-on Reset signal — — 1.39 V/ms Failure to meet this specification may cause the device to not detect reset
REG_45 VP0R+ Power-on Reset — 1.59 — V VDDIO power up/Down (See Param REG43, VDDIO Ramp Rate)
REG_45_A VP0R- Power-on Reset — 1.56 — V VDDIO Power up/Down (See Param REG43, VDDIO Ramp Rate)
REG_47 VBOR33(4) VDDIO BOD — 1.8 — V —
REG_48 VBOR12 BOR of the 1.2V regulator — 1.1 — V —
REG_48A VZPBOR33 Zero power BOR — 1.8 — V —
REG_49 VBOR33L2H BOR 3.3V low to high switch point — 1.84 — V —
REG_50 VBOR1P2L2H BOR 1.2V low to high switch point — 1.1 — V —
REG_51 VBOD12HYST_STEP VBOD12 Hysteresis step size, HYST[3:0] — 10.5 — mv —
REG_52 VBOD33HYST_STEP VBOD33 Hysteresis step size, HYST[3:0] — 51.6 — mv —
REG_53 TRST(5) External RESET valid active pulse width — 11 — µs Minimum Reset active time to guarantee MCU Reset for the module. Reset filter circuit inside Module
— 2.7 — µs Minimum Reset active time to guarantee MCU Reset for SoC with no Reset filter circuit
Note:
  1. Ferrite Bead ISAT(min) ≥ (IDDANA(max) * 1.15).
  2. Buck Inductor ISAT(min) ≥ ((ICAPACITOR + IVDDCORE_MAX) * 1.2) when the BUCK mode is enabled (shielded inductor only).
  3. User must select either LDO or BUCK Mode. The modes are exclusive to each other.
  4. VDD33 and VDDANA must be at the same voltage level.
  5. All bypass caps must be located immediately adjacent to pin(s) and on the same side of the PCB as the MCU. Each primary power supply group VDDIO, VDDANA, VDDCORE must have one bulk capacitor and all power pins with a 100 nF bypass cap.
  6. The RESET pulse width is the minimum pulse width required on the I/O pin after any filtering on the MCLR pin.
  7. Keep the DCR as low as possible to improve efficiency.
  8. These parameters are characterized but not tested in manufacturing.