The LATE register (PORTE
data latch) holds data written to port I/O pins. A write to a LATE register latches data
to corresponding port I/O pins. Those I/O port pins configured as outputs are updated. A
read from a LATE register reads the data held in the PORTE data latch, not from the port
I/O pins.
Name:
LATE
Offset:
0x430
Reset:
0x0
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
LATEx
LATEx
LATEx
LATEx
LATEx
LATEx
LATEx
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bits 0,1,2,3,4,5,6 – LATEx (x = 0 to 6; x = 0
for bit0 mapped to PE0, … x = 6 for bit6 mapped to PE6) Latch configuration for
PortE
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
