7.11.51 Change Notice Enable for PortD

This register contains the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. When CNSTYLE is set, CNEND controls the positive edge. CNEND enables a mismatch CN interrupt condition when CNSTYLE is not set

Name:	CNEND
Offset:	0x380
Reset:	0x0
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	CNENDx	CNENDx	CNENDx	CNENDx	CNENDx	CNENDx	CNENDx	CNENDx
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0,1,2,3,4,5,6,7 – CNENDx (x = 0 to 7; x = 0 for bit0 mapped to PD0, … x = 7 for bit7 mapped to PD7) Change Notice Enable for PortD

Value	Description
1	Enables a mismatch/positive edge CN interrupt condition associated with an I/O pin.
0	Disables a mismatch/positive edge CN interrupt condition associated with an I/O pin.