This register configures the
slew rate control bits associated with Port D.
Note: To configure the
slew rate, the user must also configure the SRCON0D register associated with PortD. See
Slew Rate Control Bit Settings table in the Slew Rate Control from Related
Links.
Name:
SRCON1D
Offset:
0x3D0
Reset:
0x0
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
SR1Dx
SR1Dx
Access
R/W
R/W
Reset
0
0
Bits 0,1 – SR1Dx (x = 0, 1; x = 0 for bit0
mapped to PC0, … x = 1 for bit1 mapped to PC1) Slew Rate Control 1 for
PortD
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.